#1
7th December 2015, 12:18 PM
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IIT Bombay VLSI Syllabus
Hi buddy here I am looking for EE-709: Testing and Verification of VLSI Circuits course syllabus provided by IIT Bombay, if you have then plz give me here ??
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#2
7th December 2015, 12:44 PM
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Re: IIT Bombay VLSI Syllabus
IIT Bombay offered EE-709: Testing and Verification of VLSI Circuits thought its Department of Electrical Engineering, on your demand here I am providing its syllabus: Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs. Fundamentals of VLSI testing. Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs. Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation. Design verification techniques based on simulation, analytical and formal approaches. Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation. Reference: 1. M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005 2. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985 3. M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, IEEE Press, 1994 4. M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ. Press, 2004 5. T. Kropf, Introduction to Formal Hardware Verification, Springer Verlag, 2000 Address Department of Electrical Engineering Indian Institute of Technology Bombay IIT Area, Powai Mumbai, Maharashtra 400076 |
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