#1
31st December 2016, 12:26 PM
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IIT Bombay VLSI Projects
Hi I am a new student in the IIT Bombay and I am looking for the VLSI projects so can you list me some good VLSI projects so I can have an idea??
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#2
31st December 2016, 02:15 PM
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Re: IIT Bombay VLSI Projects
Well below I have given you the list of the VLSI projects of the IIT Bombay so you can have a look Fuzzy based PID Controller using VHDL VHDL Model of Smart Sensor Design and Implementation of 32 – bit RISC Processor Design and Simulation of FFT Processor Using Radix-4 Algorithm Using FPGA Design of Multi Value Logic Using Quantum Dot Gate FET Design and Synthesis of QPSK Design and Implementation of High Speed DDR SDRAM Controller VHDL Environment for Floating Point Arithmetic Logic Unit Design and Implementation of Efficient Systolic Array Architecture VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design Design of an On-Chip Permutation Network for Multiprocessor SOC Design and Synthesis of a Field Programmable CRC Circuit Architecture Design of FPGA based 32-bit Floating Point Arithmetic Unit Fixed Angle of Rotation Using CORDIC Designs Implementation of Carry Tree Adder: Building an AMBA AHB Compliant Memory Controller Behavioral Synthesis of Asynchronous Circuits Asynchronous Transfer Mode Knockout Switch Concentrator A Multichannel Multimode RF Transceiver with DSM: AMBA-Advanced High Performance Bus IP Block: Advanced Encryption System to Improvise the System Computing Speed: Adiabatic Technique for Power Efficient Logic Circuit Design: Design and VLSI Implementation of Anti-collision Enabled Robot Processor Using RFID Technology: Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog: A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems: A Processor-In-Memory Architecture for Multimedia Compression: An Efficient VLSI Architecture for Removal of Impulse Noise in Image : Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks: A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture: A High-Speed/Low-Power Multiplier using Spurious Power Suppression Technique: An Area-Efficient Universal Cryptography Processor for Smart Cards: Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier: 3D Lifting based Discrete Wavelet Transform: |
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