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  #1  
Old 28th April 2015, 12:43 PM
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Default TE Computer Syllabus Mumbai University

I am doing B.Tech Computer Engineering Course from University of Mumbai and looking for Third Year Engineering (T.E.) - Semester V Syllabus of Computer Engineering so please provides me the same? Is it available on official website of Mumbai University?
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  #2  
Old 10th May 2018, 11:45 AM
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Default Re: TE Computer Syllabus Mumbai University

Can you provide me the syllabus/course structure of the Bachelor of Engineering - Computer Engineering Third Year Program offered by University of Mumbai?
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  #3  
Old 10th May 2018, 11:49 AM
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Default Re: TE Computer Syllabus Mumbai University

The syllabus/course structure of the Bachelor of Engineering - Computer Engineering Third Year Program offered by University of Mumbai is as follows:

Program Structure for B.E. Computer Engineering

Third Year (Computer) (Semester V)

Course Code
CPC501

Course/Subject Name
Microprocessor

Module
01 Intel 8086/8088 Architecture
1.1 8086/8088 Microprocessor Architecture, Pin Configuration, Programming Model, Memory Segmentation, Study of 8284 Clock Generator, Operating Modes, Study of 8288 Bus Controller, Timing diagrams for Read and Write operations, Interrupts.

02 Instruction Set and Programming
2.1 Instruction Set of 8086, Addressing Modes, Assembly Language Programming, Mixed Language Programming with C Language and Assembly Language.

03 System designing with 8086
3.1 Memory Interfacing: SRAM, ROM and DRAM (using DRAM Controller-Intel 8203).
3.2 Applications of the Peripheral Controllers namely 8255-PPI, 8253-PIT, 8259-PIC and 8237-DMAC. Interfacing of the above Peripheral Controllers with 8086 microprocessor
3.3 Introduction to 8087 Math Coprocessor and 8089 I/O Processor

04 Intel 80386DX Processor
4.1 Study of Block Diagram, Signal Interfaces, Bus Cycles, Programming Model, Operating Modes, Address Translation Mechanism in Protected Mode, Memory Management, Protection Mechanism.

05 Pentium Processor
5.1 Block Diagram, Superscalar Operation, Integer & Floating Point Pipeline Stages, Branch Prediction, Cache Organization.
5.2 Comparison of Pentium 2, Pentium 3 and Pentium 4 Processors. Comparative study of Multi core Processors i3, i5 and i7.

06 SuperSPARC Architecture
6.1 SuperSPARC Processor, Data Formats, Registers, Memory model Study of SuperSPARC Architecture


Syllabus B Tech Computer Engineering Third Year Program University of Mumbai




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