HDL VTU Question Papers

Can you provide me Fundamentals of HDL syllabus for EC (Electronics and Communication Engineering) 4 Semester 2010 scheme of VTU (Visvesvaraya Technological University)?

[Rajkumar Agarwal]

The Fundamentals of HDL syllabus for EC (Electronics and Communication Engineering) 4 Semester 2010 scheme of VTU (Visvesvaraya Technological University) is as follows:

Part A

Unit-1
Introduction
Why HDL? , A Brief History of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions, simulation and synthesis, Brief comparison of VHDL and Verilog

Unit-2
Data –Flow Descriptions
Highlights of Data-Flow Descriptions, Structure of Data-Flow Description, Data Type – Vectors.

Unit-3
Behavioral Descriptions
Behavioral Description highlights, structure of HDL behavioral Description, The VHDL variable –Assignment Statement,sequential statements.

Unit-4
Structural Descriptions
Highlights of structural Description, Organization of the structural Descriptions, Binding, state Machines, Generate, Generic, and Parameter statements

Part B

Unit-5
Procedures, Tasks, and Functions
Highlights of Procedures, tasks, and Functions, Procedures and tasks, Functions Advanced HDL Descriptions: File Processing, Examples of File Processing

Unit-6
Mixed –Type Descriptions
Why Mixed-Type Description? VHDL User-Defined Types, VHDL Packages, Mixed-Type Description examples

Unit-7
Mixed –Language Descriptions
Highlights of Mixed-Language Description, How to invoke One language from the Other, Mixed-language Description Examples, Limitations of Mixed-Language Description.

Unit-8
Synthesis Basics 6 hours
Highlights of Synthesis, Synthesis information from Entity and Module, Mapping Process and Always in the Hardware Domain