#1
27th July 2015, 03:06 PM
| |||
| |||
DRDO exam for Computer Science
Here I am looking for Defense Research & Development Organization (DRDO) Scientist Entry Test (SET) Computer Science and Engineering subject exam syllabus & question paper, will you please provide here???
|
#2
27th July 2015, 03:51 PM
| |||
| |||
Re: DRDO exam for Computer Science
As you are looking for Defense Research & Development Organization (DRDO) Scientist Entry Test (SET) Computer Science and Engineering subject exam syllabus & question paper, here I am giving; DRDO Scientist Entry Test (SET) Theory of Computation Digital Logic Computer Operation and Architecture programming and Data Structures Algorithms Compiler Design Operting System Data base Micro Processor Binary Number System Octal Number System Theory of Computation: Regular languages and finite automata, Context free languages and Push-down automata, Recursively enumerable sets and Turing machines, Undecidability; NP-completeness. Digital Logic: Logic functions, Minimization, Design and synthesis of combinational and sequential circuits; Number representation and computer arithmetic (fixed and floating point). Computer Organization and Architecture: Machine instructions and addressing modes, ALU and data-path, CPU control design, Memory interface, I/O interface (Interrupt and DMA mode), Instruction pipelining, Cache and main memory, Secondary storage. Programming and Data Structures: Programming in C; Functions, Recursion, Parameter passing, Scope, Binding; Abstract data types, Arrays, Stacks, Queues, Linked Lists, Trees, Binary search trees, Binary heaps. Algorithms: Analysis, Asymptotic notation, Notions of space and time complexity, Worst and average case analysis; Design: Greedy approach, Dynamic programming, Divide-and-conquer; Tree and graph traversals, Connected components, Spanning trees, Shortest paths; Hashing, Sorting, Searching. Compiler Design: Lexical analysis, Parsing, Syntax directed translation, Runtime environments, Intermediate and target code generation, Basics of code optimization. Operating System: Processes, Threads, Inter-process communication, Concurrency, Synchronization, Deadlock, CPU scheduling, Memory management and virtual memory, File systems, I/O systems, Protection and security. Databases: ER-model, Relational model (relational algebra, tuple calculus), Database design (integrity constraints, normal forms), Query languages (SQL), File structures (sequential files, indexing, B and B+ trees), Transactions and concurrency control. Computer Networks: ISO/OSI stack, LAN technologies (Ethernet, Token ring), Flow and error control techniques, Routing algorithms, Congestion control, TCP/UDP and sockets, IP(v4), Application layer protocols (icmp, dns, smtp, pop, ftp, http); Basic concepts of hubs, switches, gateways, and routers. Here is the attachment for DRDO SET CSE paper; DRDO SET CSE exam paper Section – A 1. Which of the following regular expressions describes the language- the set of all strings over {0, 1} containing at least two 1’s? A. (0+1)*11(0+1)* B. 0*110* C. 0*10*10* D. (0+1)*1(0+1)*1(0+1)* 2. Which of the following is / are regular language(s) ? I. { ambn | m , n ≥0} II. {w є {a, b}*| has equal number of a’ s and b’ s} III. {ambn | m>n} IV. {w є {a , b}* w has even number of a’ s} A. Only B. And only C. And only D. Only 3. Which of the following is true? A. For every NFA there is an equivalent PDA. B. Nondeterministic TMs are more powerful than deterministic TMs. C. DPDAs and NPDAs are equivalent in power. D. NFAs accept the class of CFLs. 4. Let L be a CFL. Then L’ must be A. CFL but not regular. B. Recursive. C. Recursively Enumerable but not Recursive. D. Regular but not CFL. 5. Which of the following is FALSE? A. CFLs are closed under union but not closed under complement. B. Regular sets are closed under intersection and Kleene Closure. C. Recursive languages are closed under intersection but not closed under complement. D. Recursively enumerable languages are closed under union and intersection. 6. Which of the following is NOT POSSIBLE? A. Finding out a minimal DFA for any arbitrary regular language. B. Constructing a deterministic TM for any arbitrary CFL. C. Determining whether two CFGs generate the same language. D. Given an arbitrary TM M (which halts on all inputs) whether the complement of the language accepted by M is recursive. 7. Which of the following is FALSE? A. Regular expressions and DFAs are equivalent. B. A DPDA cannot accept by any arbitrary CFL. C. The language accept by any TMs is a CFL. D. Complement of every regular language is CFL. 8. Consider the languages L1 and L2 given below. L1= {<M1, M2>| M1 and M2 are NFAs and L (M1 )= L (M2)} L2= {<M1, M2>| M1 and M2 are TMs and L (M1 )= L (M2)} Which of the following is true? A. L1 is undecidable but L2 is decidable. B. L2 is undecidable but L1 is decidable. C. Both L1 and L2 are undecidable. D. Both L1 and L2 are decidable. 9. Let A and B be languages corresponding to two decision problems πA and πB respectively. Let A be NP – complete problem, then hat would not B NP. Which of the following is true? A. B is NP- complete B. A proportional p B C. B proportional p A D. None of the above. 10. if there is a polynomial time algorithm for an NP- complete problem, then that would not imply which of t he following: A. P = NP B. NP = Co- NP C. P = NP ∩ Co-NP D. P NP 11. A 1KB RAM can be organized as an 8 K bit RAM. A. Using a 1 to 8 line demultiplexer. B. Using an 8 to 1 multiplexer. C. Using an 8 – input OR gate. D. None of the above. 12. A 2 KB RAM can be economically organized using- A. 64 numbers of 256 bit RAM chip and a 1/8 line decoder. B. 64 numbers of 256 bit RAM chip and a 1/64 line decoder. C. 8 numbers of 256 bit RAM chips and a 1/8 line decoder. D. 8 numbers of 256 bit RAM chips and a 1/64 line decoder 13. With reference to RETURN instruction, which of the following statement is / are true? 1. The instruction can be used only to take the flow of control back to the program from which it initially jumped. 2.The instruction retrieves the address using the current stack pointer from the stack and alters the control to the program pointed to by it. 3. The instruction works only if the registers used in the main program have been pushed and later popped before its execution. 4.The instruction can be used only in conjunction with the call instruction. A. 1st and 2nd B. 2nd only C. 1st, 2nd and 3rd only D. All the statement are true 14. In an n- CPU shared bus system, if is the probability that any CPU requests the bus in a given cycle, the probability that only one CPU uses the bus is given by- A. Nz(1-z)(n-1) B. Z(1-z)(n-1) C. N(1-z)n D. (N-1)z(1-z)n 15. A variable X has been assigned fresh values in statements numbered 6, 9 and 12 in a 25- statement program which does not have any jump instructions. This variable is used in statements numbered 7, 8, 10, 16 and 17.the statement range where the register, used by the variable X, could be assigned to some other variable are- A. 8-9, 10- 12, 17- 25 B. 11, 18-25 C. 17-25 D. Non of the above 16. If the Intel Pentium processors, was not made compatible to programs written for its predecessor, it could have been designed to be a faster processor. A. The statement is true B. The statement is false C. The speed cannot be predicted. D. Speed has nothing to do with the compatibility. 17. A certain snooping cache an snoop only an address lines. Which of the following is true? A. This would adversely affect the system if the write through protocol is used. B. This would run well if the write through protocol is used. C. Data snooping is mandatory. D. None of the above. 18. Repeated occurrence of identical interrupt during execution of this service routine can result in- A. Program error. B. Stack overflow. C. Hardware error. D. None of the above. 19. Micro programmed control is not fit for RISC architectures because- A. It tends to slow down the processor. B. It consumes more chips area. C. Handling a large number of registers is impossible in micro programmed systems. D. The 1 instruction / cycle timing requirement for RISC is difficult to achieve for all instructions. |
|