2023 2024 Student Forum > Management Forum > Main Forum

5th November 2014, 10:59 AM
Super Moderator
Join Date: Apr 2013
Re: DMRC Electronics (EC) Question Paper Delhi Metro Exam model Question Papers

Delhi Metro Rail Corporation published much recruitment for the Electrical Engineer. you are asking for the DMRC Electronics (EC) Question Paper Delhi Metro Exam model Question Papers. These are as follows:

A series RLC circuit resonates at 1000 kHz. At frequency of 995 kHz, the circuit impedance is
a) Resistive b) minimum c) Inductive d) capacitive

if each stage had gain of 10dB and noise figure of 10dB, then the overall noise figure of two-stage cascade amplifier will be
a) 10 b) 1.09 c) 1.0 d) 10.9

In SIgma delta ADC, high bit accuracy is achieved by
a) Over sampling and noise shaping b) Over sampling
C) Under sampling d) None of the above

A particular current is made up of two components: alO-A dc-and a sinusoidal current of peak value of 1.414 A. The average value of the resultant current is
a)Zero b)24.14A c)1OA d)14.14A

By doubling the sampling frequency
a) Quantisation noise decreases by 3dB
b) Quantisation noise density decreases by 3dB
c) Quantisation noise increases by 3dB
d) Quantisation noise density increases by 3dB

A Pulse train with a frequency of 1MHz Is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per Flip Flop stage
a) 100 n sec b) 50 n sec c) 20 n sec d) 10 n sec

The AID converter used in a digital voltmeter could be (1) successive approximation type (2) Flash converter type (3) Dual slope converter type. The correct sequence in the increasing order of their conversion times is
a)1,2,3 b)2,1,3 c)3,2,1 d)3,1,2

The resolution of a DIA Converter is approximately OA% 61jjjcaIe range. It is
a) An 8-bit converter b) A 10-bit converter
C) A 12 bit converter d) A 16 bit converter

in a microprocessor the resister which holds the address of the next instruction to be fetched is
a) Accumulator b) Program counter
C) Stack pointer d) Instructor register

In microcomputer WAIT states are used to
a) Make the processor wait during a DMA operation
b) Make the processor wait during a power interrupt PrOCessing
c) Make the processor wait during a power Shtd
d) Interface slow peripherals to the Processor

A 4-bit synchronous Counter uses flip4lops with propagaj delay time of 25 ns each. The maximum Possible time required for change of state will be
a) 25 ns .b) 50 ns . C) 75 ns d) 100 ns

An electromagn Wave incident on a perfect Conductor is:
a) Entirely reflected b) Fully tranSmjffj
C) Partially transmjftj d) None of these

Maximum coding gain in
a) Block Codes b) Codes
c) Turbo Codes d) RS Codes

Noise figure of an amplifier depends on
a) Bandwidth b) Output power c) Power input d) None of the above

BCH code belongs to
a) Block Codes b) Codes
c) Turbo Codes d) None of the above

When a carrier is phase modulated, with an integrated modulating signal, the resultant is
a) Phase modulated signal b) Frequency modulated signal
C) Amplitude modulated signal d) QPSK modulated signal

A satellite orbiting in 600 km orbit transmits 5 GHz frequency. The Doppler shift observed at the ground station, when the satellite is over head of the station is
d) None of the
a) Zero b) Maximum c) Infinity

A communication channel disturbed by additive white Gaussian noise has a bandwidth of 4kHz and SNR of 15. The highest transmission rate that such a channel can support (in k-bits/sec) is
a)16 b)1.6 c)3.2 d)60

An inductor supplied with 50 V ac with a frequency of 10 kHz passes a current of 7.96 mA. The value ofinductor is
a) lmH b) lOmH c) lOOmH d) IH

In a capacitor, the electric charge is stored in
a) Dielectric b) Metal plates
c) Dielectric as well as metal plates d) Neither dielectric nor metal plates

Oscillator requires
a) No feedback b) Negative feedback
c) Positive feedback d) Either positive or negative

Which loss in a transformer varies significantly with load?
a) Hysteresis loss b) Eddy current loss
C) Copper loss d) Core loss

When L is doubled and C is halved, the resonance frequency of series tuned circuit becomes
a) Doubled b) Halved C) One quarter d) Unchanged

In a Series resonant circuit, with the increase in L
a) Resonant frequency will decrease
b)’ Bandwidth will decrease
c) Q will increase
d) AN of these

Quick Reply
Your Username: Click here to log in


Thread Tools Search this Thread

All times are GMT +5. The time now is 02:58 PM.

Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2024, vBulletin Solutions Inc.
SEO by vBSEO 3.6.0 PL2

1 2 3 4