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  #1  
2nd May 2015, 12:23 PM
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CSE 7th Sem Syllabus MDU

I am the student of the B.Tech of Computer Science & Engineering 7th Semester of Maharshi Dayanand University, Rohtak and I want to download the complete syllabus of it with the exam pattern so can you please provide me the same so that I can start my preparation of exam?
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  #2  
27th April 2018, 10:06 AM
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Re: CSE 7th Sem Syllabus MDU

I want the syllabus of B.Tech Computer Science & Engineering 7th semester of Maharshi Dayanand University, Rohtak so can you provide me?
  #3  
27th April 2018, 10:09 AM
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Join Date: Aug 2012
Re: CSE 7th Sem Syllabus MDU

I am providing you the syllabus of B.Tech Computer Science & Engineering 7th semester of Maharshi Dayanand University, Rohtak

MDU B.Tech Computer Science & Engineering 7th semester syllabus

Course No. Subject
CSE-401 F Advanced Computer Architecture
CSE-403 F Software Project Management
(CSE, I T)
CSE-405 F Compiler Design
CSE-407 F Neural Networks
CSE-409 F Advanced Java
(CSE, IT) Deptt Elective
CSE-411 F Compiler Design Lab
CSE-413F Neural NetworksUsing MATLAB
CSE-415F AdvancedJAVA Lab(CSE, IT)
CSE-417F PRATICAL TRAINING-II

List of Electives

1 IT-421F Embedded Systems Design
2 IT-471F Management I nfo r matio n Systems
4 IT-407 F Web Engineering
5 MATHE-302 F Operations Research (Commonwith IT 6th Semester)
6 CSE-423 F Distributed Operating System
7 IT-465F Network Security & Management
8 CSE-425F Digital Image Processing
9 CSE-435F Advanced Database Management Systems
10 CSE-437F Natural Language Processing
11 CSE-439F Object Oriented System Development
12 IT-467 F Computer Software Testing
13 IT-469F Logic & Functional Programming
14 CSE-441 F Human Computer Interaction
15 IT-473F High Speed Networks

ADVANCED COMPUTER ARCHITECTURE

Section A

Architecture And Machines: Some defi nit ion and t erms, int erpr etation and micr opr ogramming. The instruction set, Basic
data t y pe s, Instructions, Addressing and Memor y . Virtual to real mapping. Basic Instr uction Timi ng.
Time, Area And Instruction Sets: Time , co st -area, t ec hnol o gy state of the Art, The Economi cs of a processor proj ec t: A
study , I nstruction se t s, Professor Evaluation Matrix
Section B
Cache Memory Notion: Basic No ti on, Cache Organization, Cac he Data, adjusting the data for cache o r gani zation, wri t e
poli ci es, st rategies f or line r eplacement at miss t i me, Cache Envir onment, other ty pes of Cache. Split I and D-Cac hes, on
chip cache s, Two level Caches, writ e assembl y Cache, Cache r eferences per ins t ructi on, technology dependent Cache
considerations, v i rtual to r eal t ransl ation, overlapping the Tcycl e in V-R Translation, studi es. Design summar y .
Section C
Memo ry System Design: The phy si cal memor y , model s of simpl e pr ocesso r memor y intera cti on, processor memor y
mode ling using queuing theo r y , open, closed and mixed-queue models, waiting time , perfo rmance , and buff ersize, revi ew
and se l ection of queuing mode l s, proc essors with cache.
Section D
Concurrent Processors: Vec t or Processors, Vector Memor y , Multiple Issue Machines, Comparing vec t or and Multiple
Issue pr ocesso rs.
Shared Memory Multiprocessors: Basi c issues, parti tioning , sy nchr onization and coher ency , Ty pe of shar ed Memor y
mult i processors, Memo r y Coher ence in shar edMemo r y Mul tipr ocesso r s.
Tex t Book:
Advance comput er ar chit ect ur e by Hwang & Briggs, 1993, TMH.
Ref erence Books:
Pipelinedand Parallel processor design by Michael J. Fiy nn 1995, Narosa


MDU B.Tech Computer Science & Engineering 7th semester syllabus






Contact

Maharshi Dayanand University
Delhi Road, University Secretariat, Rohtak, Haryana 124001
01262 393 596

For complete syllabus here is the attachment


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