Verilog Training

I want to do Designing with Verilog training course from Xilinx so can y6ou please provide me the details of this course?

[Shaleen]

Xilinx is the world’s leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3D ICs, enabling the next generation of smarter, connected, and differentiated systems and networks.

Designing with Verilog

This comprehensive course is a thorough introduction to the Verilog language.

The emphasis is on writing Register Transfer Level (RTL) and behavioral source code.

This class addresses targeting Xilinx devices specifically and FPGA devices in general.

In this three-day course, you will gain valuable hands-on experience.

Level FPGA 1

Training Duration 3 days

Who Should Attend?
Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisites

Basic digital design knowledge

Software Tools

Vivado® Design or System Edition 2015.3

Hardware

Architecture: N/A*
Demo board: Kintex®-7 FPGA KC705 board*

Course Outline

Day 1

Hardware Modeling Overview
Verilog Language Concepts
Modules and Ports
Demo: Multiplexer
Lab 1: Building Hierarchy
Introduction to Testbenches
Lab 2: Verilog Simulation and RTL Verification

Day 2

Verilog Operators and Expressions
Continuous Assign Statements
Lab 3: Memory
Verilog Procedural Statements
Lab 4: Clock Divider and Address Counter
Controlled Operation Statements
Lab 5: n-bit Binary Counter and RTL Verification

Day 3

Verilog Tasks and Functions
Advanced Language Concepts
Finite State Machines
Lab 6 Finite State Machines
Targeting Xilinx FPGAs
Lab 7: Implement and Download
Advanced Verilog Testbenches
Lab 8: Using Verilog File I/O