M.Tech 1-2sem R13 Syllabus jntuk

[bharunaughty]

pls attach m.tech 1st year 2nd sem syllabus jntuk cse branch with all the electives in detailed

Can you provide me the syllabus M. Tech in Electronics and Communications Engineering (ECE) Program offered by Jawaharlal Nehru Technological University: Kakinada?

[pawan]

The syllabus M. Tech in Electronics and Communications Engineering (ECE) Program offered by Jawaharlal Nehru Technological University: Kakinada is as follows:

I Year I Semester

DIGITAL SYSTEM DESIGN
UNIT-I: Minimization Procedures and CAMP Algorithm:
Review on minimization of switching functions using tabular methods, k-map, QM algorithm, CAMP-I algorithm, Phase-I: Determination of Adjacencies, DA, CSC, SSMs and EPCs,, CAMPI algorithm, Phase-II: Passport checking,Determination of SPC, CAMP-II algorithm: Determination of solution cube, Cube based operations, determination of selected cubes are wholly within the given switching function or not, Introduction to cube based algorithms.

UNIT-II: PLA Design, Minimization and Folding Algorithms:
Introduction to PLDs, basic configurations and advantages of PLDs, PLA-Introduction, Block diagram of PLA, size of PLA, PLA design aspects, PLA minimization algorithm(IISc algorithm), PLA folding algorithm(COMPACT algorithm)-Illustration of algorithms with suitable examples.

UNIT -III: Design of Large Scale Digital Systems:
Algorithmic state machinecharts-Introduction, Derivation of SM Charts, Realization of SM Chart, control implementation, control unit design, data processor design, ROM design, PAL design aspects, digital system design approaches using CPLDs, FPGAs and ASICs.

UNIT-IV: Fault Diagnosis in Combinational Circuits:
Faults classes and models, fault diagnosis and testing, fault detection test, test generation, testing process, obtaining a minimal complete test set, circuit under test methods- Path sensitization method, Boolean difference method, properties of Boolean differences, Kohavi algorithm, faults in PLAs, DFT schemes, built in self-test.

UNIT-V: Fault Diagnosis in Sequential Circuits:
Fault detection and location in sequential circuits, circuit test approach, initial state identification, Haming experiments, synchronizing experiments, machine identification, distinguishing experiment, adaptive distinguishing experiments.

TEXT BOOKS:
1. Logic Design Theory-N. N. Biswas, PHI
2. Switching and Finite Automata Theory-Z. Kohavi , 2nd Edition, 2001, TMH
3. Digital system Design using PLDd-Lala

REFERENCE BOOKS:
1. Fundamentals of Logic Design Charles H. Roth, 5th Ed., Cengage Learning.
2. Digital Systems Testing and Testable Design MironAbramovici, Melvin A. Breuer and Arthur D. Friedman- John Wiley & Sons Inc


Syllabus M. Tech in ECE by Jawaharlal Nehru Technological University: Kakinada