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6th February 2013, 11:44 AM
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| JNTU Hyderabad M.Tech Previous Question Papers
I want the previous question papers of the M.tech of JNTU can you please help me. We have papers for the following subjects CAD CAM MANUFACTURING METHODS AND MECHANICS OF COMPOSITES R09 SE ADVANCED DATA STRUCTURES AND ALGORITHMS R13 OBJECT ORIENTED MODELING R09 COMPUTER SYSTEM DESIGN R09 TE ADVANCED OPTIMIZATION TECHNIQUES AND APPLICATIONS R13 CS IMAGE PROCESSING AND PATTERN RECOGNITION R09 EPS ADVANCED OPTIMIZATION TECHNIQUES AND APPLICATIONS R13 DESIGN FOR MANUFACTURING ASSEMBLY R09 CAD CAM MECHATRONICS R09 GE ADVANCED SOIL MECHANICS R13 AMS AUTOMATION IN MANUFACTURING R13 CONTROL ADVANCED CONTROL SYSTEMS R13 JAVA AND WEB TECHNOLOGIES R09 ENVIRONMENTAL COMPUTER PROGRAMMING AND NUMERICAL METHODS R13 TE TRAFFIC ENGINEERING AND MANAGEMENT R13 CAD CAM FINITE ELEMENT ANALYSIS R09 DIGITAL DIGITAL SYSTEM DESIGN R13 CAD CAM NUMERICAL METHODS FOR PARTIAL DIFFERENTIAL EQUATION R09 PRECISION ENGINEERING R09 SEP 2010 PE THEORY OF METAL CUTTING R13 CS SOFTWARE ARCHITECTURE AND DESIGN PATTERNS R09 V2 CS ADVANCED DATA STRUCTURES AND ALGORITHMS R13 CAD CAM STRESS ANALYSIS AND VIBRATION R09 CS ADVANCED COMPUTER ARCHITECTURE R09 SE COMPUTER ORIENTED NUMERICAL METHODS R13 CS SOFTWARE ARCHITECTURE AND DESIGN PATTERNS R09 CONTROL EMBEDDED SYSTEMS R09 MRE ADVANCED ELECTROMAGNETIC THEORY R13 CS SOFTWARE QUALITY ASSURANCE AND TESTING R09 ADVANCED MECHANICS OF SOLIDS R09 ADVANCED PROBLEM SOLVING R09 As you are asking for Jawaharlal Nehru Technological University (JNTU) Hyderabad M.Tech VLSI system design Low Power VLSI Design Previous year Question Paper: Code No: 54206/MT M.Tech. II-Semester Examinations, August/September-2007. LOW POWER VLSI DESIGN (Embedded Systems, Digital Electronics & Communication Systems and VLSI System Design) Time: three hours Max. Marks: 60 ans any 5 ques. All ques. carry equal marks - - - 1.a] elaborate the different advantages and limitations of the Siliconon- Insulator Technology ? b] discuss about shallow Trench Isolation (SIT) technique. 2.a] How threshold Voltage adjustments can be carried out for CMOS devices? discuss with the help of necessary equations. b] With the help of sketches discuss about the RetrogradeWell CMOS process. 3. define the Low Voltage, Low- power CMOS SOI process. 4.a] define the dynamic characteristics of MOS transistor, using necessary equations. b] define the characteristics of Secondary MOS FET behavior. 5. Draw the circuit for commonEmitter Bi CMOS driver configuration and discuss its characteristics. 6. discuss about the characteristics of Bi CMOS a] Circuits utilizing lateral p-n-p BJTs in PMOS structures. b] provide the performance valuation of merged Bi CMOS logic gates. How the weak points of conventional Bi CMOS logic gates are overcome by these circuits ? 7.a] discuss about the Functionality Theme and Synchronous themes of latches and Flip Flops. b] elaborate the Performance measures of latches and FlipFlops. 8. Write notes on any 2 a] MOSFET in a Hybrid mode environment. b] ESDfree Bi CMOS c] Bipolar SPICE Model   Last edited by sumit; 19th November 2019 at 08:01 AM. |