IIT Bombay High Performance Computing

Hello sir I am here as I want to get the list of the Projects of High Performance Computing Lab (HPC Lab) of IIT Bombay so will you please provide me the list??

[Pathak]

High Performance Computing Lab (HPC Lab) was established in 2008 at Department of Electrical Engineering, IIT Bombay, with initial support from Tata Consultancy Services Ltd.

It is since then being convened by Professor Sachin Patkar. The lab is located in the Annexe building of the Department.


Projects of this Lab:

Ongoing Projects

GPGPU based parallelization of Bremics(Bombay Relaxation MOS Integrated Circuit Simulator )
Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi, Yogesh Save and Abhijit Joshi.

High Performance Navier-Stokes CFD solver using GPU and Multicore Processors
Investigators: Prof. Sachin Patkar, Prof. Saravanan Vijayakumaran Nishant Shelar and Mandar Gurav.
Sponsored by VSSC, ISRO.

Approximate solution of combinatorial optimization problems using electrical network analysis
Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi and Yogesh Save.
Sponsored by VLSI Consortium.

Exploration of New Communication Methods for Many-core VLSI Systems
Investigators: Prof. Sachin Patkar and Hrishikesh Sharma.
Sponsored by Tata Consultancy Services Ltd..

System for Parallel Matrix-vector Computations.
Investigators: Prof. Sachin Patkar and Prof. Shreeniwas Sapre.
Sponsored by Intel Corp.

High Performance Computing using GPU, FPGA and Multicore Processors.
Investigators: Prof. Sachin Patkar, Prof. Rajbabu Velmurugan, Prof. Saravanan Vijayakumaran and Prof. Dinesh Kumar Sharma
Sponsored by Naval Research Board, India.

Accelerating performance analysis of Photo-voltaic cell arrays of arbitrary geometry, using two-graph method based circuit simulator.
Investigators: Dr. Gaurav Trivedi, Dr. Mahesh B. Patil, Dr. S. Patkar and Dr. H. Narayanan

Topological Network Transformation based parallel circuit simulator using manycore/multicore processors.
Investigators: Dr. Gaurav Trivedi, Prof. Sachin Patkar and Prof. H. Narayanan

Accelarating accurate nerve conduction analysis, using modified two-graph method
Investigators: Dr. Gaurav Trivedi, Dr. S. Patkar and Dr. H. Narayanan

Development of a ESL-level Synthesis tool for a class of VLSI Systems based on Projective Geometry
Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Utkarsh Gupta.
In collaboration with Tata Consultancy Services Ltd..

Prototyping of a Projective Geometry-based On-chip Network for CMP VLSI Systems.
Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Chiraag Juvekar.
In collaboration with Tata Consultancy Services Ltd..


Finished Projects

Modified Nodal Analysis(MNA) based circuit simulator using LU decomposition – GPGPU based parallelization of non linear circuit updation with devices having non-linear VI characteristics
Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi, Ajay Gopal Kannampallil and Abhijit Joshi.

CUDA Based Acceleration of Haptic Rendering
Investigators: Prof. Subhasis Chaudhuri, Prof. Sachin Patkar, Abhijit Joshi and Mandar Gurav.

High Performance Navier-Stokes CFD solver using GPU and Multicore Processors
Investigators: Dr. Sachin B. Patkar, Dr. Rajbabu Velmurugan, Dr. Saravanan Vijayakumaran, Dr. Gaurav Trivedi and Dr. Praveen Nair
Consultancy Project with VSSC, Indian Space Research Organization..

Scientific Computation on Graphics Processing Unit using CUDA
Investigators: Prof. Sachin Patkar and Pradip Panchal.
In collaboration with Computational Research Labs.

A System for Error Control Coding using Expander-like codes and its Applications
Investigators: Prof. Sachin Patkar, Swadesh Choudhary and Hrishikesh Sharma.

In collaboration with Tata Consultancy Services Ltd..
Accelerating Double Precision Sparse Matrix Vector Multiplication on FPGAs
Investigators: Prof. Sachin Patkar, Sumedh Attarde and Sunil Puranik.
In collaboration with Computational Research Labs.

Applications of Projective Geometry in Computing and Communications
Investigators: Prof. Sachin Patkar, Abhishek Patil, Dr. B.S. Adiga and Hrishikesh Sharma.
Sponsored by Tata Consultancy Services Ltd..

FPGA Design for Decoder of Projective Geometry(PG)-based Low Density Parity Check(LDPC) Codes
Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Nachiket Gajare.
Sponsored by Tata Consultancy Services Ltd..

FPGA-based High Performance Double-Precision Matrix Multiplication
Investigators: Prof. Sachin Patkar, V.B.Y. Vinay Kumar, Siddharth Joshi and Sunil Puranik.
In collaboration with Computational Research Labs.


Facilities:
• High-end Computers (No. 23)
• Server (No. 7)
o Xeon based (No. 3)
o Opteron based (No. 4)
• Desktops (No. 16)
o High End (No. 5)
o Medium End (No. 4)
o Lower End (No. 7)
• Nvidia Graphics Processing Unit for Parallel processing (No. 17)
• Tesla Series cards (No. 2)
• High End GTX series cards (No. 9)
• Lower End GTX series cards (No. 6)
• FPGA Boards (No. 15)
• Nallatech PCI-Express enabled board (No. 1)
• Xilinx Boards (No. 11)
o Spartan 3E boards (No. 8)
o XUPV5-LX110T boards (Virtex 5) (No. 3)
• Altera Boards (No. 1)
o DE2-70 board
• Dini Boards (No. 2)

Contact Detail:
High Performance Computing Lab
2nd Floor,
Department of Electrical Engineering Annexe,
Indian Institute of Technology
Powai, Mumbai 400076
Ph: +91-22-2576 4408
FAX: +91-22-2572 3707
eMail: hpc@ee.iitb.ac.in