#1
25th July 2014, 10:27 AM
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Delhi Metro Rail Corporation Junior Engineer previous year question papers
Will you please share with me the Delhi Metro Rail Corporation Junior Engineer previous year question papers?
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#2
25th July 2014, 12:16 PM
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Re: Delhi Metro Rail Corporation Junior Engineer previous year question papers
As you want to get the Delhi Metro Rail Corporation Junior Engineer previous year question papers so here it is for you: 1.The number of digits in octal system is a.8 b.7 c.10 d. none 2..The number of digits in Hexadecimal system is a.15 b.17 c.16 d. 8 3.The number of bits in a nibble is a.16 b.5 c.4 d.8 4.The digit F in Hexadecimal system is equivalent to —— in decimal system a.16 b.15 c.17 d. 8 5.Which of the following binary numbers is equivalent to decimal 10 a.1000 b.1100 c.1010 d.1001 6.The number FF in Hexadecimal system is equivalent to —— in decimal system a.256 b.255 c.240 d.239 7.IC s are a. analog b. digital c. both analog and digital d. mostly analog 8.The rate of change of digital signals between High and Low Level is a. very fast b. fast c. slow d. very slow 9. Digital circuits mostly use a. Diodes b. Bipolar transistors c. Diode and Bipolar transistors d. Bipolar transistors and FETs 10.Logic pulser a. generates short duration pulses b. generate long duration pulses c. generates long and short duration d. none of above 11.What is the output state of an OR gate if the inputs are 0 and 1? a.0 b.1 c.3 d.2 12.What is the output state of an AND gate if the inputs are 0 and 1? a.0 b.1 c.3 d.2 13.A NOT gate has… a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 14.An OR gate has… a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 15.The output of a logic gate can be one of two _____? a. Inputs b. Gates c.States d. none 16.Logic states can only be ___ or 0. a. 3 b. 2 c.1 d.0 17.The output of a ____ gate is only 1 when all of its inputs are 1 a. NOR b. XOR c. AND d. NOT 18.A NAND gate is equivalent to an AND gate plus a …. gate put together. a. NOR b. NOT c. XOR d. none 19.Half adder circuit is ______? a. Half of an AND gate b. A circuit to add two bits together c. Half of a NAND gate d. none of above 20. Numbers are stored and transmitted inside a computer in a. binary form b. ASCII code form c. decimal form d. alphanumeric form 21.The decimal number 127 may be represented by a. 1111 1111B b. 1000 0000B c. EEH d. 0111 1111 22.. A byte corresponds to a. 4 bits b. 8 bits c. 16 bits d. 32 bits 23.A gigabyte represents a.1 billion bytes b. 1000 kilobytes c. 230 bytes d. 1024 bytes 24. A megabyte represents a. 1 million bytes b. 1000 kilobytes c. 220 bytes d. 1024 bytes 25.. A Kb corresponds to a. 1024 bits b. 1000 bytes c.210 bytes d. 210 bits 26.A parity bit is a. used to indicate uppercase letters b. used to detect errors c. is the first bit in a byte d. is the last bit in a byte 27. Which of these devices are two state. a. lamp b. punched card c. magnetic tape d. all the above The output impedance of of a logic pulser is a. low b. high c. may be low or high d. none of above 28.The number of LED display indicators in logic probe are a.1 b.2 c.1 or 2 d.4 29.In hexadecimal number system,A is equal to decimal number a.10 b.11 c.17 d.18 30.Hexadecimal number F is equal to octal number a.15 b.16 c.17 d.18 31.Hexadecimal number E is equal to binary number a.1110 b.1101 c.1001 d.1111 32.Binary number 1101 is equal to octal number a.15 b.16 c.17 d.14 33.Octal number 12 is equal to decimal number a.8 b.11 c.9 d. none 34.Decimal number 10 is equal to binary number a.1110 b.1000 c.1001 d.1010 35.Binary number 110011011001 is equal to decimal number a.3289 b.2289 c.1289 d.289 36.1111+11111= a.101111 b.101110 c.111111 d.011111 37.Binary multiplication 1*0= a.1 b.0 c.10 d.11 38.110012 -100012= a.10000 b.01000 c.00100 d.00001 39.10112*1012= a.55 b.45 c.35 d.25 40.1110112*100012= a.111101101 b.111101100 c.111110 d.1100110 41.4 bits is equal to a. 1 nibble b.1 byte c. 2 byte d. none of above 42. which is non-volatile memory a. RAM b. ROM c. both d. none 43. The contents of these chips are lost when the computer is switched off? a. ROM chips b. RAM chips c. DRAM chips d. none of above 44.What are responsible for storing permanent data and instructions.? a. RAM chips b. ROM chips c. DRAM chips d. none of above 45. Which parts of the computer perform arithmetic calculations? a. ALU b. Registers c. Logic bus |
#3
17th March 2015, 12:27 PM
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Re: Delhi Metro Rail Corporation Junior Engineer previous year question papers
Sir, please forward me previous year paper of the Delhi Metro Rail Corporation Junior Engineer as soon as possible?
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#4
17th March 2015, 01:13 PM
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Re: Delhi Metro Rail Corporation Junior Engineer previous year question papers
You need not mention stream of Junior Engineer post exam. Here, I am giving you previous year paper of the Junior Engineer (Electronics) conducted by Delhi Metro Rail Corporation. If you want some other paper let me know I will give you. A series RLC circuit resonates at 1000 kHz. At frequency of 995 kHz, the circuit impedance is a) Resistive b) minimum c) Inductive d) capacitive if each stage had gain of 10dB and noise figure of 10dB, then the overall noise figure of two-stage cascade amplifier will be a) 10 b) 1.09 c) 1.0 d) 10.9 In SIgma delta ADC, high bit accuracy is achieved by a) Over sampling and noise shaping b) Over sampling C) Under sampling d) None of the above A particular current is made up of two components: alO-A dc-and a sinusoidal current of peak value of 1.414 A. The average value of the resultant current is a)Zero b)24.14A c)1OA d)14.14A By doubling the sampling frequency a) Quantisation noise decreases by 3dB b) Quantisation noise density decreases by 3dB c) Quantisation noise increases by 3dB d) Quantisation noise density increases by 3dB A Pulse train with a frequency of 1MHz Is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per Flip Flop stage a) 100 n sec b) 50 n sec c) 20 n sec d) 10 n sec The AID converter used in a digital voltmeter could be (1) successive approximation type (2) Flash converter type (3) Dual slope converter type. The correct sequence in the increasing order of their conversion times is a)1,2,3 b)2,1,3 c)3,2,1 d)3,1,2 The resolution of a DIA Converter is approximately OA% 61jjjcaIe range. It is a) An 8-bit converter b) A 10-bit converter C) A 12 bit converter d) A 16 bit converter in a microprocessor the resister which holds the address of the next instruction to be fetched is a) Accumulator b) Program counter C) Stack pointer d) Instructor register In microcomputer WAIT states are used to a) Make the processor wait during a DMA operation b) Make the processor wait during a power interrupt PrOCessing c) Make the processor wait during a power Shtd d) Interface slow peripherals to the Processor A 4-bit synchronous Counter uses flip4lops with propagaj delay time of 25 ns each. The maximum Possible time required for change of state will be a) 25 ns .b) 50 ns . C) 75 ns d) 100 ns An electromagn Wave incident on a perfect Conductor is: a) Entirely reflected b) Fully tranSmjffj C) Partially transmjftj d) None of these Maximum coding gain in a) Block Codes b) Codes c) Turbo Codes d) RS Codes Noise figure of an amplifier depends on a) Bandwidth b) Output power c) Power input d) None of the above BCH code belongs to a) Block Codes b) Codes c) Turbo Codes d) None of the above When a carrier is phase modulated, with an integrated modulating signal, the resultant is a) Phase modulated signal b) Frequency modulated signal C) Amplitude modulated signal d) QPSK modulated signal A satellite orbiting in 600 km orbit transmits 5 GHz frequency. The Doppler shift observed at the ground station, when the satellite is over head of the station is d) None of the a) Zero b) Maximum c) Infinity A communication channel disturbed by additive white Gaussian noise has a bandwidth of 4kHz and SNR of 15. The highest transmission rate that such a channel can support (in k-bits/sec) is a)16 b)1.6 c)3.2 d)60 An inductor supplied with 50 V ac with a frequency of 10 kHz passes a current of 7.96 mA. The value ofinductor is a) lmH b) lOmH c) lOOmH d) IH In a capacitor, the electric charge is stored in a) Dielectric b) Metal plates c) Dielectric as well as metal plates d) Neither dielectric nor metal plates Oscillator requires a) No feedback b) Negative feedback c) Positive feedback d) Either positive or negative Which loss in a transformer varies significantly with load? a) Hysteresis loss b) Eddy current loss C) Copper loss d) Core loss When L is doubled and C is halved, the resonance frequency of series tuned circuit becomes a) Doubled b) Halved C) One quarter d) Unchanged In a Series resonant circuit, with the increase in L a) Resonant frequency will decrease b)’ Bandwidth will decrease c) Q will increase d) AN of these |
#5
28th November 2015, 03:42 PM
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]Sir, please forward me previous year paper mech.of the Delhi Metro Rail Corporation Junior Engineer as soon as posible
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#6
7th February 2016, 09:01 PM
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Re: Delhi Metro Rail Corporation Junior Engineer previous year question papers
how can i get all previous year paper of dmrc electronics for jen
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