#1
5th November 2014, 04:28 PM
| |||
| |||
Chip Designing Course after 12th
Hi I want to know the courses offered by Smart Chip Design?
|
#2
6th November 2014, 09:35 AM
| |||
| |||
Re: Chip Designing Course after 12th
Smart Chip Design is a VLSI Training Institute in Bangalore focused on Protocol Based Training in Advanced VLSI Design & Verification. Courses Offered- ASIC Verification-AV- Course Fee- Rs 12,000 /- Duration - 3 Months Course Structure- 1 Advanced Verilog HDL 2Advanced Verification using systemverilog 3ASIC Verification Concepts 4Verification IP Development 5PROJECTS : Module(IP) Level Verification Project Project#1 : Verilog mini project Project Project#2 : SystemVerilog Based Complex Project Project#3 : SystemVerilog Based Complex Project (AXI, UART,USB, MemCtrl, Bridge, etc) Advanced VLSI Design-AVD Course Fee- Rs 8,000 /- Duration - 2 Months Course Structure- 1Advanced Digital Design 2VHDL ‐ Language and Coding for Synthesis 3Verilog ‐ Language and Coding for Synthesis 4RTL Verification 5FPGA Design Methodology and Prototyping 6Project ASIC Design and Verification- ADV Course Fee- Rs 20,000 /- Duration - 6 Months Course Structure- 1VLSI Design Flow 2Advanced Digital Design 3Advanced Digital Design using verilog HDL 4On-Chip Bus Protocols (AXI4.0, OCP3.0) 5Peripheral Bus Protocols(USB3.0/PCIEx Gen3) 6Advanced Verilog for Verification 7SystemVerilog for Advanced Verification 8ASIC Verification Concepts 9ASIC Verification Methodologies : OVM 10PROJECTS : Module(IP) Level Verification Projects Project#1 : Verilog Based RTL Project based Complex project Project#2 : SystemVerilog Based Project based Complex IP (USB, PCIEx, MemCtrl, Bridge, etc) Project#3 :SV & OVM/UVM Based Project based on Complex IP (UART, KBD, Bridge, etc) Project#4 :SV & OVM/UVM Based Project based on Complex IP (Ethernet, DMA, Bridge, etc) 11Interview Question Kit |