#1
13th November 2014, 04:14 PM
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Chennai Anna University VLSI question papers?
Will you please tell me from where I can get the question papers of the Chennai Anna University VLSI can you please give me that???????
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#2
14th November 2014, 08:35 AM
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Re: Chennai Anna University VLSI question papers?
As you are telling that you want to get the Chennai Anna University VLSI question papers so, I am providing you that. Here is the attachment for the question paper of VLSI Chennai Anna University you can download that and some of the questions are given below. 1. DRAW THE IV CHARACTERISTICS OF MOS TRANSISTOR. 2. BREIF THE DIFFERENT OPERATING REGIONS OF MOS SYSTEM. 3. DRAW THE EQUIVALENT CIRCUIT STRUCTURE OF LEVEL 1 MOSFET MODEL IN SPICE. 4. BRIEF ABOUT THE VARIATION OF FRINGING FIELD FACTOR WITH THE INTERCONNECT GEOMETRY. 5. COMPARE CMOS COMBINATIONAL LOGIC GATES WITH REFERENCE TO THE EQUIVALENT N-MOS DEPLETION LOAD LOGIC WITH REFERENCE TO THE AREA REQUIREMENT. 6. WHAT ARE THE ADVANTAGE OF USING A PSEUDO N-MOS GATE INSTEAD OF A FULL CMOS GATE 7. WHAT ARE THE FACTORS THAT CAUSE TIMING FAILURES? 8. WHAT ARE THE ADVANTAGE OF A SINGLE STUCK AT FAULT? 9. WITH COMPONENT INSTANTITATION, WRITE A VHDL PROGRAM FOR A BUFFER. 10. WRITE A NOTE ON TRANSPORT DELAY. 11. (A) Discuss In Detail About: (1) Full-Custom Mask Layout Design (8) (2) Cmos Inverter Layout Design (8) [Or] (B) (I) With A Neat Diagram Discuss In Detail About Dc Transfer Characteristics Of Cmos. (8) (Ii) Write A Short Notes On The Following Along With The Mask View (I) Oxide Related Capacitance (4) (Ii) Junction Capacitance (4) 12. (A) (I) Obtain An Expression For Level 2 Model Equation Of Mosfet In Spice. (8) (Ii) Discuss In Detail About: (1) Variation Of Mobility With Electric Field. (2) Variation Of Channel Length In Saturation Modes. (3) Saturation Of Carrier Velocity. (8) [Or] (B)(I) How Do The Spice Mosfet Model Account For The Parasitic Device Capacitances?(8) (Ii) Explain The Charecterization Of Circuits.(8) 13. (A) (I)For A Two Input Nand Gate Derive An Expression For The Drain Current. (8) (Ii) Draw A Cmos Nor2 Gate And Its Complementary Operation With Necessary Equations. (4) (Iii) Obtain A Cmos Logic Design Realizing The Boolean Function Z=A(D+E)+Bc (8) [Or] (B) (I) Draw A Circuit Diagram Of The Cmos Sr Latch And Explain In Detail. (8) (Ii) Along With The Necessary Input And Output Waveforms Of The Cmos Dff Negative Edge Triggered Master Slave D Flip Flop. (8) 14. (A) (I) Explain Indetail About Partition And Mux Testing With Necessary Example And Diagram. (8) (Ii) Explain The Principle Of Silicon Debug. (8) [Or] (B) (I) Elaborate The Scan Based Techniques. (8) (Ii) Discuss In Detail About: (I) Pseudo Random Pattern Generator. (4) (Ii) Output Response Analyser. (4) 15. (A) Using Mixed Level Mode Write A Vhdl Program For A (I) Comparator. (8) (Ii) D –Flip Flop. (8) [Or] (B) With All The Three Types Of Modeling Write A Vhdl Program For A (I) Decoder (8) (Ii) Full Adder. (8) I think that this answer will helpful to you….. |